Many integrated circuits (ICs) require a highly accurate, e.g., less than 1% deviation, frequency source. A conventional design of such a source includes a phase-locked loop (PLL) and a tightly controlled, reference clock. High accuracy requires frequent updating to prevent drift. However, even a single bad update can create an intolerable frequency error. For example, in the context of writing and reading data to and from computer storage disks, the write signal has about a ±1% frequency deviation tolerance. If the frequency of the write signal deviates beyond this tight tolerance, data written after the out-of-tolerance deviation will be corrupted and data may not be successfully read back.
Noise on chipset boards and from sources within ICs themselves creates an environment where the frequency source can be corrupted once every billion or so cycles—in many systems, this equates to many times day. This corruption can cause the input of an on-chip PLL to experience a large phase disturbance, which causes frequency instability. Reducing corruption is becoming more and more challenging as the level of integration continues to increase and signal voltages continue to decrease. For example, radio frequency circuits onboard system-on-chip ICs or chip-set boards exacerbate the noisy environment. In addition, most all ICs/chip-set boards contain multiple clock domains that increase the chance that noise from multiple sources will combine to cause false switching events. Decreasing signal voltage decreases noise margin on both internal and external signals, making the low-voltage signals more susceptible to corruption causing disturbances.
A conventional approach to highly accurate frequency synthesis in the presence of a noisy reference clock is to redesign the integrated circuit/system to limit/eliminate noise sources or interference. Drawbacks to this approach include: difficulties changing the design depending on the time in the product cycle; on-board filtering, if appropriate, can be an expensive solution and take up valuable space; tools for predicting noise are typically inaccurate and pessimistic; the redesign can be very time consuming and debug intensive; and multiple redesigns may be needed before achieving acceptable results. Another conventional approach is to tighten the loop characteristics of the PLL to limit the exposure to noise-induced disturbances. Drawbacks to this approach include the fact that the loop tightening may impact desired loop dynamics and the difficulty of predicting/modeling noise characteristics. Yet another conventional approach to highly accurate frequency synthesis in the presence of a noisy reference clock is to tighten the requirements on the reference clock networks. Drawbacks to this approach include: increased design time; reference clock networks are not as capacitive (noise resistant) as clock networks; filtering schemes may create slow rise time characteristics that can create skew/jitter concerns; and the difficulty of predicting/modeling noise characteristics.
FIGS. 1A-C illustrate the effect of a noisy reference clock signal REF_CLK on a conventional PLL frequency synthesizer 100 and on the resulting synthesized output signal SYN_OUT. Referring first to FIG. 1A, synthesizer 100 includes a charge pump/loop filter/voltage controlled oscillator (VCO) 104 controlled by a phase detector 108 coupled to a “numerator” frequency divider 112 and a “denominator” frequency divider 116. Charge pump/loop filter/VCO 104 has an internal voltage control signal V_CONTROL that drives the VCO so as to generate SYN_OUT signal. Phase detector 108 controls charge pump/loop filter/VCO 104 via V_CONTROL signal using an increase-voltage signal INC_OUT and a decrease-voltage signal DEC_OUT. Numerator frequency divider 112 divides fed-back SYN_OUT signal by a divide-by value “N” to provide a NDIV_OUT signal, and denominator frequency divider 116 divides REF_CLK signal by a divide-by value “D” to provide a DDIV_OUT signal. Consequently, the frequency of SYN_OUT signal equals the frequency of REF_CLK signal multiplied by N and divided by D.
FIG. 1A includes a timing diagram 120 showing the waveforms 124,128,132, 136,140, respectively, of NDIV_OUT, DDIV_OUT, INC_OUT, DEC_OUT and V_CONTROL signals when the PLL portion of synthesizer 100 is stable, i.e., locked onto a clean REF_CLK signal. Note how the leading edges 124A, 128A of the NDIV_OUT and DDIV_OUT signals, respectively, line up with one another so that the pulses 132A, 136A in INC_OUT and DEC_OUT signals are fully aligned so as to cancel each other, thereby resulting in no change to V_CONTROL signal. Thus, there is no change to the frequency of the SYN_OUT signal.
FIG. 1B illustrates the effect of a noisy environment (e.g., chip board, system on chip, etc.) on an originally clean REF_CLK signal waveform 146A that results in a corrupt REF_CLK signal waveform 146B containing a triggering-edge-type glitch 148, i.e., an anomaly in the waveform having edges 148A-B capable of triggering or otherwise impacting the operation of electronic devices (not shown) in the manner that any of the normal, clean-signal edges 150A-D would affect such devices. For example, an edge-triggered latch that latches on a rising normal edge, such as edges 150A, 150C, would likewise latch on a rising edge of a glitch, e.g., rising edge 148B of glitch 148. It is noted that glitch 148 is denoted a “negative” glitch since it occurs in an otherwise high portion of waveform 146B. Although not shown, a “positive” glitch would be an opposite glitch that occurs in a low portion of waveform 146B.
Clean REF_CLK signal waveform 146A is generated by a reference clock driver 152 and travels through a reference clock network 156 to a reference clock receiver 160. Along its way through network 156, clean REF_CLK signal waveform 146A is subject to electrical noise from various sources 164 that can combine (as represented by summer 168) into a noise signal 172 that can cause receiver 160 to falsely switch and cause glitch 148 in corrupt REF_CLK signal waveform 146B. Corrupt REF_CLK signal waveform 146B would then be the input to frequency synthesizer 100 illustrated more particularly in FIG. 1A, which would, in turn, generate an out-of-specification SYN_OUT signal 176 that could cause various faults in circuitry, such as circuitry 178, that is responsive to the SYN_OUT signal.
FIG. 1C shows a timing diagram 180 for conventional PLL frequency synthesizer 100 of FIG. 1A when REF_CLK signal is corrupted by a glitch, such as glitch 148 of FIG. 1B. As seen, the glitch causes the leading edges 182A-B, 184A-B, respectively, of waveforms 182, 184 of NDIV_OUT and DDIV_OUT signals to be misaligned so that the signals are out of phase with each other, i.e., have a phase offsets 186A-B. Consequently, a correction to SYN_OUT signal to account for phase offsets 186A-B is made via changes in waveform 188 of V_CONTROL signal due to the mismatched pulses 190A-B, 192A-B of waveforms 190, 192 of INC_OUT and DEC_OUT signals, respectively. Absent the glitch in REF_CLK signal, waveform 188 of V_CONTROL would have been unchanged so that the frequency of SYN_OUT signal would have remained unchanged. However, the glitch has caused frequency synthesizer 100 to change the phase alignment and/or frequency of SYN_OUT signal, potentially to an extent that causes one or more faults in circuitry 178 (FIG. 1B) responsive to the SYN_OUT signal.